"FPGA designers will be able to achieve timing closure more quickly by directly reading the industry-standard SDC timing constraint format into TimeQuest timing analyzer," said Lonn Fiance, director of Strategic Alliances at Synopsys. "Adoption of the SDC format will increase productivity among FPGA designers and further advance the deployment of a standard timing verification methodology across the semiconductor industry."

Powerful Productivity Enhancements

With this latest version of Quartus II software, Altera introduces new technology advancements to meet customer requirements at 90 nm and set the stage for the 65-nm process node. Highlights of these new features include:

     --  TimeQuest timing analyzer:  A new, ASIC-strength timing analyzer
         providing comprehensive support for the industry-standard SDC format.
         TimeQuest timing analyzer enables users to create, manage, and
         analyze designs with complex timing constraints, such as
         clock-multiplexed designs and source synchronous interfaces, and to
         quickly perform advanced timing verification. TimeQuest timing
         analyzer is available in Quartus II software version 6.0 subscription
         edition.
     --  Expanded team-based design support:  A design feature that includes a
         project manager interface for managing resource and timing budgets at
         the top-level design. Additionally, the project manager interface
         allows the designer to manage timing constraints between blocks to
         maximize performance. This new feature allows teams to collaborate on
         the design of high-density FPGAs, resulting in improved team
         productivity and increased performance between design blocks. This
         feature builds upon the incremental compilation design features first
         introduced in Quartus II software version 5.0.
     --  SystemVerilog support:  Allows faster register transfer level (RTL)
         implementation by supporting design constructs of the popular IEEE
         1800-2005 Standard SystemVerilog syntax hardware description and
         verification language.
     --  Enhanced I/O pin planner:  Provides easier integration of Altera's
         intellectual property and simpler pin assignments.
     --  Expanded board-level design support:  Offers HSPICE models of
         Stratix(R) II single-ended outputs for more efficient board modeling.

    Performance Leadership

Quartus II software continues to offer designers a full speed grade advantage for high-density 90-nm designs and up to a three speed grade advantage for low-cost 90-nm designs compared to the nearest competitor.

"For designers racing to market with complex, high-density, high-performance FPGA designs, Quartus II software delivers unparalleled advantages. It offers the most reliable path to productivity and performance today as the industry designs at 90 nm and prepares for 65 nm," said Chris Balough, Altera's director of software and Nios(R) marketing. "Customers continue to rely on Altera to deliver advanced technology in our Quartus II software, such as TimeQuest timing analyzer, to help them easily develop powerful designs in the shortest time possible."

For more information about Quartus II software, visit www.altera.com/quartus2. To learn more about TimeQuest timing analyzer and additional Quartus II features, visit the Quartus II software online demo page at www.altera.com/verificationtraining.

Pricing and Availability

Both the subscription edition and the web edition of Quartus II software version 6.0 are now available. The subscription edition is shipping to all customers with an active software subscription. The free Quartus II web edition software can be downloaded at www.altera.com/q2webedition. Altera's software subscription program simplifies the process of obtaining Altera(R) design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive the Quartus II software subscription edition, the ModelSim(R) Altera edition and a full license to the IP Base Suite-nine of Altera's most popular intellectual property cores (DSP, memory and Gigabit Ethernet MAC cores). The annual software subscription is $2,000 for a node-locked PC license. Quartus II design software supports major operating systems, including Windows XP Professional x64, Windows XP; Windows 2000; Sun Solaris 8 and 9; and Red Hat Linux Enterprise 3.0 and 4.0. New or existing customers may obtain a software subscription from Altera distributors worldwide.

About Altera

Altera's programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate, and win in their markets. Find out more at www.altera.com.

NOTE: Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder.

     Editor Contact:
     Kelly St. Denis
     Altera Corporation
     408-544-6397
     Email Contact

CONTACT: Kelly St. Denis of Altera Corporation, +1-408-544-6397, or
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